Bonjour,
la compilation est ok.
Par contre, lorsque je lance la simulation, j'ai une erreur du type:
vsim work.test_bench work.sinus work.is_main
# vsim work.test_bench work.sinus work.is_main
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.test_bench(test)
# ** Fatal: (vsim-3370) Top-level design unit 'sinus' must be an ENTITY, CONFIGURATION , MODULE or PROGRAM
# Time: 0 ps Iteration: 0 Instance: / File: NOFILE
# FATAL ERROR while loading design
# Error loading design
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.sinus.all;
-----
entity is_main is
port(
impulsion : in std_logic;
clock : in std_logic;
retard : in std_logic_vector (3 downto 0);
wave_out : out std_logic_vector (4 downto 0)
);
end entity;
-----
architecture main of is_main is
signal comptage : std_logic_vector (3 downto 0);
signal b : integer :=0;
-----
begin
-----
process
-----
begin
b<=to_integer(unsigned(retard) );
wait until impulsion'event and impulsion='1';
for i in 0 to b loop
wait until clock'event;
comptage<=comptage+1;
end loop;
comptage<="0000";
end process;
-----
process
variable table_value:table_value_type;
variable table_index:table_index_type;
-----
begin
while comptage=retard loop
for i in 0 to max_table_index loop
table_value:=get_table_value(t able_index);
table_index:=table_index+1;
--wave_out<=table_value;
wave_out<=std_logic_vector(to_ unsigned(table_value,sine_vect or_type'length));
wait until clock'event;
end loop;
table_index:=0;
end loop;
end process;
-----
end architecture main;
---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----
entity test_bench is
end entity;
-----
architecture test of test_bench is
signal impulsion : std_logic :='0';
signal clock : std_logic :='0';
signal retard : std_logic_vector (3 downto 0) :="1110";
-----
component is_main is
port(
impulsion : in std_logic;
clock : in std_logic;
retard : in std_logic_vector (3 downto 0);
wave_out : out std_logic_vector (4 downto 0)
);
end component;
-----
begin
porte : is_main
port map(impulsion=>impulsion,clock =>clock,retard=>retard);
-----
process
begin
wait for 60 ns;
impulsion<='1';
wait for 10 ns;
impulsion<='0';
end process;
-----
process
begin
wait for 1 ns;
clock<='1';
wait for 1 ns;
clock<='0';
end process;
-----
end architecture test;
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----
package sinus is
constant max_table_value:integer:=5;
subtype table_value_type is integer range 0 to max_table_value;
constant max_table_index:integer:=5;
subtype table_index_type is integer range 0 to max_table_index;
subtype sine_vector_type is std_logic_vector (4 downto 0);
function get_table_value (table_index:table_index_type) return table_value_type;
end;
-----
package body sinus is
function get_table_value (table_index:table_index_type) return table_value_type is
variable table_value:table_value_type;
begin
case table_index is
when 0 =>
table_value:=0;
when 1 =>
table_value:=1;
when 2 =>
table_value:=2;
when 3 =>
table_value:=3;
when 4 =>
table_value:=4;
when 5 =>
table_value:=5;
end case;
return table_value;
end;
end;
-----------------------------------
Quelle est la source d'erreur ? Je ne vois pas !
Cordialement
DELALIN Ambroise
-----