erreur dans application de test du périphérique

[invite75d4f504]

Bonjour
Je suis entrain de réaliser un projet sous EDK qui consiste à créer une IP personnalisé.
Cette IP consiste à réaliser une multiplication de deux nombres a et b.
D’abord, je commence par la création de la plateforme de base par l'outil BSB, ensuite il s'agit de la création et l'importation du périphérique personnalisé par l'outil Create or import peripheral et ceci est fait avec succès.
Enfin, j'ai ajouté une application software par la création d'un fichier en code C qui permet de tester l'IP personnalisé.
Lorsque je désire créer le bitstream (download.bit et system.bit) pour l'envoyer par la suite au FPGA, je trouve des erreurs dans l'application software de test de périphérique.
Aidez-moi pour corriger ce code s'il vous plait.
Voici le code C de l'application C:
#include "xparameters.h"
#include "multiply.h"
int main (void)
{ int a , b, num1, num2, product;
print ( "Strat multiply ...\n\r");
for (a=16,b=1,a>0;a--,b++)
{
MULTIPLY_mWriteReg(XPAR_MULTIP LY_0_BASEADDR,0,a);
num1 = MULTIPLY_mReadReg(XPAR_MULTIPL Y_0_BASEADDR,0);
MULTIPLY_mWriteReg(XPAR_MULTIP LY_0_BASEADDR,0x4,a);
num1 = MULTIPLY_mReadReg(XPAR_MULTIPL Y_0_BASEADDR,0x4);
product=MULTIPLY_mReadReg(XPAR _MULTIPLY_0_BASEADDR,0x8);
xil_printf("%d *%d =%d \n\r" ,num1 ,num2, product);
}
print ("multiply Done ...\n\r");
return 0;

}
Lorsque je fais Device Configuration ->Update Bitstream avant de saisir le code, j’obtiens les fichiers system.bit et download.bit.
Les erreurs trouvées lorsque je répète Device Configuration ->Update Bitstream après la saisie du code C.

/cygdrive/c/DOCUME~1/EMNAEL~1/LOCALS~1/Temp/cc8FIbHA.o: In function `main':
/cygdrive/c/VIRTEX4/exercise5/SourcesC/code.c:9: undefined reference to `xil_io_out32'
/cygdrive/c/VIRTEX4/exercise5/SourcesC/code.c:11: undefined reference to `xil_io_in32'
/cygdrive/c/VIRTEX4/exercise5/SourcesC/code.c:16: undefined reference to `xil_io_out32'
/cygdrive/c/VIRTEX4/exercise5/SourcesC/code.c:18: undefined reference to `xil_io_in32'
/cygdrive/c/VIRTEX4/exercise5/SourcesC/code.c:20: undefined reference to `xil_io_in32'
collect2: ld returned 1 exit status
make: *** [test/executable.elf] Error 1

Ci-joint les fichiers multiply.h ,xparameters.h et le user_logic.vhd

-----

[farouk77]

Bonjour,


1) il n'y a rien en fichier joint

2) dans la ligne 5 de ton code "print ( "Strat multiply ...\n\r");" t'es sur que c'est "print" et pas "printf" (la fonction que t'utilises fait partie d'une de tes bibliothèques ou c'est juste une erreur? )


Sinon sans les bibliothèques je ne peux rien dire d'autre ^^

[invite75d4f504]

bonjour
merci pour votre réponse ;print est juste et voila les pièces jointes
xparameters.h


/* Description: Driver parameters*/

#define STDIN_BASEADDRESS 0x84000000
#define STDOUT_BASEADDRESS 0x84000000
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral RS232_UART */
#define XPAR_RS232_UART_BASEADDR 0x84000000
#define XPAR_RS232_UART_HIGHADDR 0x8400FFFF
#define XPAR_RS232_UART_DEVICE_ID 0
#define XPAR_RS232_UART_BAUDRATE 115200
#define XPAR_RS232_UART_USE_PARITY 0
#define XPAR_RS232_UART_ODD_PARITY 0
#define XPAR_RS232_UART_DATA_BITS 8
/* Canonical definitions for peripheral RS232_UART */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_UARTLITE_0_HIGHADDR 0x8400FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN -1
/* Definitions for driver MULTIPLY */
#define XPAR_MULTIPLY_NUM_INSTANCES 1

/* Definitions for peripheral MULTIPLY_0 */
#define XPAR_MULTIPLY_0_DEVICE_ID 0
#define XPAR_MULTIPLY_0_BASEADDR 0xC0A00000
#define XPAR_MULTIPLY_0_HIGHADDR 0xC0A0FFFF
* Definitions for peripheral XPS_BRAM_IF_CNTLR_0 */
#define XPAR_XPS_BRAM_IF_CNTLR_0_BASEA DDR 0xFFFF0000
#define XPAR_XPS_BRAM_IF_CNTLR_0_HIGHA DDR 0xFFFFFFFF
/* Definitions for bus frequencies */
#define XPAR_CPU_PPC405_DPLB0_FREQ_HZ 100000000
#define XPAR_CPU_PPC405_IPLB0_FREQ_HZ 100000000
/****************************** ****************************** ******/

/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/****************************** ****************************** ******/

#define XPAR_CPU_PPC405_CORE_CLOCK_FRE Q_HZ 100000000
#define XPAR_PPC405_VIRTEX4_CORE_CLOCK _FREQ_HZ 100000000

/****************************** ****************************** ******/

#define XPAR_CPU_ID 0
#define XPAR_PPC405_VIRTEX4_ID 0
#define XPAR_PPC405_VIRTEX4_DPLB0_DWID TH 64
#define XPAR_PPC405_VIRTEX4_DPLB0_NATI VE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_DWID TH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_NATI VE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_DWID TH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_NATI VE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_DWID TH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_NATI VE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR _BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR _HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR _BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR _HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_FASTEST_PL B_CLOCK DPLB0
#define XPAR_PPC405_VIRTEX4_GENERATE_P LB_TIMESPECS 1
#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IDCR_BASEA DDR 0x00000100
#define XPAR_PPC405_VIRTEX4_IDCR_HIGHA DDR 0x000001FF
#define XPAR_PPC405_VIRTEX4_DISABLE_OP ERAND_FORWARDING 1
#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
#define XPAR_PPC405_VIRTEX4_DETERMINIS TIC_MULT 0
#define XPAR_PPC405_VIRTEX4_PLBSYNCBYP ASS 1
#define XPAR_PPC405_VIRTEX4_APU_CONTRO L 0b1101111000000000
#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.b"

/****************************** ****************************** ******/



multiply.h

/****************************** ****************************** *****************
* Filename: C:\VIRTEX4\exercise5/drivers/multiply_v1_00_a/src/multiply.h
* Version: 1.00.a
* Description: multiply Driver Header File
* Date: Fri Oct 29 13:34:30 2010 (by Create and Import Peripheral Wizard)
****************************** ****************************** *****************/

#ifndef MULTIPLY_H
#define MULTIPLY_H
#include "xbasic_types.h"
#include "xstatus.h"
#include "xio.h"
#define MULTIPLY_USER_SLV_SPACE_OFFSET (0x00000000)
#define MULTIPLY_SLV_REG0_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000000)
#define MULTIPLY_SLV_REG1_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000004)
#define MULTIPLY_SLV_REG2_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000008)
#define MULTIPLY_mWriteReg(BaseAddress , RegOffset, Data) \
xil_io_out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
#define MULTIPLY_mReadReg(BaseAddress, RegOffset) \
xil_io_in32((BaseAddress) + (RegOffset))

#define MULTIPLY_mWriteSlaveReg0(BaseA ddress, RegOffset, Value) \
xil_io_out32((BaseAddress) + (MULTIPLY_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
#define MULTIPLY_mWriteSlaveReg1(BaseA ddress, RegOffset, Value) \
xil_io_out32((BaseAddress) + (MULTIPLY_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
#define MULTIPLY_mWriteSlaveReg2(BaseA ddress, RegOffset, Value) \
xil_io_out32((BaseAddress) + (MULTIPLY_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))

#define MULTIPLY_mReadSlaveReg0(BaseAd dress, RegOffset) \
xil_io_in32((BaseAddress) + (MULTIPLY_SLV_REG0_OFFSET) + (RegOffset))
#define MULTIPLY_mReadSlaveReg1(BaseAd dress, RegOffset) \
xil_io_in32((BaseAddress) + (MULTIPLY_SLV_REG1_OFFSET) + (RegOffset))
#define MULTIPLY_mReadSlaveReg2(BaseAd dress, RegOffset) \
xil_io_in32((BaseAddress) + (MULTIPLY_SLV_REG2_OFFSET) + (RegOffset))

XStatus MULTIPLY_SelfTest(void * baseaddr_p);

#endif /** MULTIPLY_H */

--------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Sun Oct 24 18:24:11 2010 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_commo n_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 3
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);

attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 2);
signal slv_reg_read_sel : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;

begin

--USER logic implementation added here

MUL_PROC rocess(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset ='1' then
slv_reg2 <= (others=> '0');
else
slv_reg2 <= slv_reg0 * slv_reg1 ;
end if;
end if;
end process MUL_PROC;


------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 2);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 2);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2);

-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');

else
case slv_reg_write_sel is
when "100" => slv_reg0 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1 );
when "010" => slv_reg1 <= Bus2IP_Data(0 to C_SLV_DWIDTH-1 );
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2 ) is
begin

case slv_reg_read_sel is
when "100" => slv_ip2bus_data <= slv_reg0;
when "010" => slv_ip2bus_data <= slv_reg1;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');

IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';

end IMP;

[farouk77]

Bonjour

#define XPAR_MULTIPLY_0_BASEADDR

Il n'y a pas d'espace dans le nom de la constante, alors que dans ton code:

MULTIPLY_mWriteReg(XPAR_MULTIP LY_0_BASEADDR,0,a);

Des espaces ont été rajoutés un peu partout dans le code, le compilateur ne reconnaît pas le nom des constantes

tout comme dans le fichier multiply.h:

#define MULTIPLY_SLV_REG0_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000000)
#define MULTIPLY_SLV_REG1_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000004)
#define MULTIPLY_SLV_REG2_OFFSET (MULTIPLY_USER_SLV_SPACE_OFFSE T + 0x00000008)

Il n'y a pas d'espace entre le T et le E (OFFSET)..

voila voila Je pense que l'erreur vient de là ^^

[A voir en vidéo sur Futura]

[invite75d4f504]

Bonjour



Il n'y a pas d'espace dans le nom de la constante, alors que dans ton code:



Des espaces ont été rajoutés un peu partout dans le code, le compilateur ne reconnaît pas le nom des constantes

tout comme dans le fichier multiply.h:



Il n'y a pas d'espace entre le T et le E (OFFSET)..

voila voila Je pense que l'erreur vient de là ^^

je vais corriger et je vous dis le résultat

[invite75d4f504]

je vais corriger et je vous dis le résultat

le même problème existe ,d'ailleurs les espaces n'existe pas dans mon projet il s'agit ici de faute de frappe.

[invite75d4f504]

Bonjours à tous , j'ai trouver cette solution sur le web , est ce que quelqu'un peut m'aider à exploiter ces information je ne comprend pas...



http://www.xilinx.com/support/answers/37617.htm


AR #37617 - 12.1 EDK - undefined reference to 'xil_io_out32'
12.1 EDK - undefined reference to 'xil_io_out32'
Description
I am using the "Create and Import Peripheral" function in XPS, I create a
peripheral that contains one or more software addresss, I enable registers
using the "User logic software register" tick-box. The following error occurs
when the automatically created drivers compile:
./src/helloworld.o: In function 'main':
/cygdrive/c/Projects/MDB-
3/Motorcontrol/Platform/SDK/Software_v1_0_a/hello_world_0/Debug/../src/helloworld.c:41:
undefined reference to 'xil_io_out32'
collect2: ld returned 1 exit status
make: *** [hello_world_0.elf] Error 1
Solution
You need to change the drivers from xil_io_out32 to either XIo_In32 or XIo_Out32. This problem is scheduled to be fixed in 12.4.
AR #37617 - 12.1 EDK - undefined reference to 'xil_io_out32'12.1 EDK - undefined reference to 'xil_io_out32'DescriptionI am using the "Create and Import Peripheral" function in XPS, I create aperipheral that contains one or more software addresss, I enable registersusing the "User logic software register" tick-box. The following error occurswhen the automatically created drivers compile:./src/helloworld.o: In function 'main':/cygdrive/c/Projects/MDB-3/Motorcontrol/Platform/SDK/Software_v1_0_a/hello_world_0/Debug/../src/helloworld.c:41:undefined reference to 'xil_io_out32'collect2: ld returned 1 exit statusmake: *** [hello_world_0.elf] Error 1SolutionYou need to change the drivers from xil_io_out32 to either XIo_In32 or XIo_Out32. This problem is scheduled to be fixed in 12.4.