VHDL - erreurs dans code RTL

[invitebf051ef0]

Bonjour,
Je dois faire un code vhdl qui consiste à calculer la racine carrée d'un nombre Nbits. J'ai fait le code suivant:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
   
entity sqrootop is
   generic (NBITS: natural);
   port (
      arg          : in  std_logic_vector(NBITS-1 downto 0);
      roundup      : in  std_logic;
      rroot        : out std_logic_vector(NBITS-1 downto 0));
end entity sqrootop;

architecture rtl of sqrootop is
    signal mask, remainder: unsigned(NBITS-1 downto 0);
    signal sig: unsigned(NBITS-1 downto 0);
begin

   process (arg,roundup)  
  
   begin
       mask <= 2**(NBITS-2);
       sig <= (OTHERS => '0');
       remainder <= arg;
       while (mask /= 0) loop
           if ((sig+mask) <= remainder) then
               remainder <= remainder - (sig + mask);
               sig <= sig + (mask sll 1);
           end if;
           sig <= sig srl 1;
           mask <= mask srl 2;
       end loop;
       
       if (remainder > sig and roundup) then
           sig <= sig +1;
       end if;
   end process;
  
  rroot <= sig;
   
end rtl;

Mais quand je compile, j'obtiens les erreurs suivantes...

 ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(26): Type error resolving infix expression "**" as type ieee.numeric_std.unsigned.
# ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(28): Signal "arg" is type ieee.std_logic_1164.std_logic_vector; expecting type ieee.numeric_std.unsigned.
# ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(38): No feasible entries for infix operator "and".
# ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(38): Type error resolving infix expression "and" as type std.standard.boolean.
# ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(43): Signal "sig" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic_vector.
# ** Error: /da2/users/edatp/edatp39/HSM1_08_MT/HDL/RTL/sqroot_comb.vhd(45): VHDL Compiler exiting

Quelqu'un pourrait-il m'aider à les résoudre?
Merci
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