Hi,
I am trying to synthesize a filter and it works out fine in Xilinx ISE
9.1i for Synthesize and Implement.However when I create a test
bench and try to see a Post-Place & Route simulation result, I get
warnings about unbound components. Following is the warning and the
snippet of code that Im using.What am I doing wrong here....Any help
is appreciated!!!
I am getting the following warnings(a lot of them) when I synthesize
the following code for the filter. What am I doing wrong?
On a post translate or a post place and route simulation, I get a 'U'
on my output pin...
The error I see looks something like
# ** Warning: (vsim-3473) Component instance 'tt_out_0_obuf : x_obuf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_0_output_off_o1inv : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_0_output_off_oceinv : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_0_output_off_omux : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_0_output_otclk1inv : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_1_obuf : x_obuf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_1_output_off_o1inv : x_inv' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_1_output_off_oceinv : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd
# ** Warning: (vsim-3473) Component instance 'tt_out_1_output_off_omux : x_buf' is not bound.
# Time: 0 ps Iteration: 0 Region: /tt_tbw_vhd/uut File: C:/Xilinx91i/PFE/test/netgen/par/tt_timesim.vhd....
and so on
Code snippet for filter:
****************************** ********************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filter is
Port ( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
filter_in : in std_logic;
filter_out : out std_logic_vector (13 downto 0)
);
end filter;
architecture Behavioral of filter is
-- Filter Order
constant K : integer := 18;
-- New types to use
type tab6x13 is array (5 downto 0) of signed (12 downto 0); -- 6 coefficients under 13 bits
type tab6x15 is array (5 downto 0) of signed (14 downto 0); -- 6 additions under 15 bits
type tab6x28 is array (5 downto 0) of signed (27 downto 0); -- 6 multiplications under 28 bits
type tab19x14 is array (K downto 0) of signed (13 downto 0); -- shifted inputs under 14 bits
-- Intermediate signals
signal COEFF : tab6x13;
signal REG1,REG2 : tab19x14;
signal SUM : tab6x15;
signal PROD : tab6x28;
-- Input buffer
signal INPUT : std_logic_vector (13 downto 0);
-- Output buffer
signal OUTPUT : signed (13 downto 0);
-- Temporary signals
signal sum1_1 : signed (28 downto 0);
signal sum1_2 : signed (28 downto 0);
signal sum1_3 : signed (28 downto 0);
signal sum2 : signed (29 downto 0);
signal sum3 : signed (30 downto 0);
begin
main : process (clk, rst, en)
begin
if (rst = '1') then
COEFF(5) <= to_signed (33, 13);
COEFF(4) <= to_signed (-78, 13);
COEFF(3) <= to_signed (172, 13);
COEFF(2) <= to_signed (-376, 13);
COEFF(1) <= to_signed (1283, 13);
COEFF(0) <= to_signed (2048, 13);
INPUT <= (others => '0');
filter_out <= (others => '0');
REG1(K) <= (REG1(K)'range => '0');
REG2(K) <= (REG2(K)'range => '0');
elsif (CLK'event and CLK = '1') then
if (en = '1') then
if (filter_in = '0') then
INPUT <= '11111111111111';
else
INPUT <= '00000000000001';
end if;
REG1(K) <= signed(INPUT);
REG2(K) <= signed(INPUT);
filter_out <= std_logic_vector(OUTPUT);
end if;
end if;
end process main;
shifting:for j in K-1 downto 0 generate
stages: process(rst,clk,en)
begin
if (rst='1') then
REG1(j) <= (REG1(j)'range=>'0');
REG2(j) <= (REG2(j)'range=>'0');
elsif (clk'event and clk = '1') then
if (en = '1') then
REG1(j) <= REG2(j+1);
REG2(j) <= REG1(j+1);
end if;
end if;
end process;
end generate;
summing : for j in 9 downto 5 generate
SUM(j-4) <= REG1(2*j)(13) & REG1(2*j) + REG1(K - 2*j);
end generate;
SUM(0) <= REG1(9)(13)®1(9);
multiplying : for j in 5 downto 0 generate
PROD(j) <= SUM(j)*COEFF(j);
end generate;
-- Tree adder
sum1_1 <= PROD(5)(27) & PROD(5) + PROD(4);
sum1_2 <= PROD(3)(27) & PROD(3) + PROD(2);
sum1_3 <= PROD(1)(27) & PROD(1) + PROD(0);
sum2 <= sum1_1(28) & sum1_1 + sum1_2;
sum3 <= sum2(29) & sum2 + sum1_3;
OUTPUT <= sum3(13 downto 0);
end Behavioral;
****************************** ********************
Thanks in advance.
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