Vhdl tri-state

[invite9cb0a5df]

Bonjour !!

Voilà je suis en train d'écrire un petit programme en vhdl, j'avais pris un tri-state comme exemple sur internet que j'ai un peu changé !
Enfin je l'ai juste clocké pour éviter d'avoir des conlits sur ma sortie.
Voici le code:

entity Mux_mem_addr is
Port ( 
       out_mux 		        : out STD_LOGIC_VECTOR (8 downto 0);
       clk			        : in  std_logic;
       sel 				: in  STD_LOGIC_vector (1 downto 0);
       in1				: in  STD_LOGIC_VECTOR (8 downto 0);
       in2				: in  STD_LOGIC_VECTOR (8 downto 0));
end Mux_mem_addr;

architecture Behavioral of Mux_mem_addr is
begin
P1: process (clk)
begin
   if clk'event and clk='1' then  
				out_mux <= in1 when (sel(0) = '1')
				else(others => 'Z');
				out_mux <= in2 when (sel(1) = '1') 
				else (others => 'Z');
				out_mux <= ( others => 'L' );      
   end if;
end process P1;

Mes erreurs se rerouvent aux lignes que j'ai surligné. Franchement je n'arrive pas à saisir le problème!

Voici le code erreur:

Line 48: Syntax error near "when".
Line 50: Syntax error near "when".

Je vous remercie de votre attention !
Bonne journée
-----

[invite9cb0a5df]

J'ai trouvé comment il fallait l'écrire voici le code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tri_state_instruct is
Port ( out_mux 		: out STD_LOGIC_VECTOR (8 downto 0);
         sel 				: in  STD_LOGIC_vector (7  downto 0);
         in2				: in  STD_LOGIC_VECTOR (8 downto 0);
         in1				: in  STD_LOGIC_VECTOR (53 downto 0));
end tri_state_instruct;

architecture Behavioral of tri_state_instruct is

begin
			out_mux <= "000000000" 		when sel(0) = '1' else (others => 'Z');
			out_mux <= in2				when sel(1) = '1' else (others => 'Z');
			out_mux <= in1(53 downto 45)	when sel(2) = '1' else (others => 'Z');
			out_mux <= in1(44 downto 36) 	when sel(3) = '1' else (others => 'Z');
			out_mux <= in1(35 downto 27)	when sel(4) = '1' else (others => 'Z');
			out_mux <= in1(26 downto 18) 	when sel(5) = '1' else (others => 'Z');
			out_mux <= in1(17 downto  9)	when sel(6) = '1' else (others => 'Z');
			out_mux <= in1(8  downto  0) 	when sel(7) = '1' else (others => 'Z');


end Behavioral;

Voilà j'espère que cela pourra aider des gens
Bonne journée!!