Code VHDL Digital filter (issue with multiplication)

**ykhalildie** · 26/09/2014, 10h47

Hi everyone,

Je suis nouveau en VHDL, et je dois implémenter un filtre digital (butterworth: 2 cells d'ordre 2 en serie).

Je suis entrain de me confronter à l'implémentation d'un filtre digital, l'algorithme est bon, mais je ne sais pas pourquoi mon programme me pose des problèmes lorsque je souhaite executer une multiplication.

J'utilise la librairie USE IEEE.numeric_std.ALL pour effectuer les oppérations.

Les données sont typées en virgule fixe 32Q18.

Voici le code (beaucoup de ligne pour pas grand chose...)

D'autre part, la multiplication de deux grandeurs en virgule fixe double le nombre de bits, j'ai effectué une remise au format du résultat a la main...

Ma question est donc de savoir pourquoi la multiplication ne passe pas, sachant que du point de vue syntax le code est bon.

j'ai essayé de déclarer mes données en "signed" a la place de "STD_LOGIC_VECTOR" et de multiplier comme ceci:

Code:

result = signed(a) * signed(b)

mais le checking syntax me ramène des erreurs directement.

Je suis evidemment ouvert à tout autre commentaires, j'espère qu'il y en aura.

Merci par avance.

-ykhalildie

Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;



entity Filter1_Vo is
port (
    Filter_IN : in STD_LOGIC_VECTOR (31 DOWNTO 0);
    Filter_OUT : out STD_LOGIC_VECTOR (31 DOWNTO 0);
    RST : in STD_LOGIC;
    CLK_Filter : in STD_LOGIC
);
end Filter1_Vo;
architecture Behavioral of Filter1_Vo is

  CONSTANT G1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011110101010011001"; 
  CONSTANT a21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011100111111111111"; 
  CONSTANT a31 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011101110110000100"; 
  CONSTANT G2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000010110010011000001"; 
  CONSTANT a22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000010101000011011111"; 
  CONSTANT a32 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000100001000100011"; 
  CONSTANT b2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000010000000000000000000";
  
  SIGNAL Input_REG : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";  
  SIGNAL Cell1_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL Output_REG : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";  

  SIGNAL temp : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp1 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp2 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp3 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";

  SIGNAL temp02 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp12 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp22 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp32 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";


  SIGNAL E1_0 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E1_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E1_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S1_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S1_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL E2_0 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E2_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E2_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S2_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S2_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL a31mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL a21mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul11 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum11 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum12 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul12 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum13 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL a32mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL a22mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum23 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

begin

input_reg_process : PROCESS (CLK_Filter, RST)
  BEGIN
    IF RST = '0' THEN
        Cell1_OUT <= "00000000000000000000000000000000";
        Output_REG <= "00000000000000000000000000000000";
        Input_REG <= "00000000000000000000000000000000";
        E1_0 <= "00000000000000000000000000000000";
        E1_1 <= "00000000000000000000000000000000";
        E1_2 <= "00000000000000000000000000000000";
        E2_0 <= "00000000000000000000000000000000";
        E2_1 <= "00000000000000000000000000000000";
        E2_2 <= "00000000000000000000000000000000";
        S1_1 <= "00000000000000000000000000000000";
        S1_2 <= "00000000000000000000000000000000";
        S2_1 <= "00000000000000000000000000000000";
        S2_2 <= "00000000000000000000000000000000";
    ELSIF CLK_Filter'event AND CLK_Filter = '1' THEN
        Input_REG <= Filter_IN;
        E1_2 <= E1_1;
        E1_1 <= E1_0;
        S1_2 <= S1_1;
        
        E2_2 <= E2_1;
        E2_1 <= E2_0;
        S2_2 <= S2_1;
        



     ------------------ Section 1 ------------------
E1_0 <= Input_REG;

--a31mul <= a31*S1_2;
temp <= a31 * S1_2;
a31mul(31) <= temp(49);
a31mul(30) <= temp(48);
a31mul(29) <= temp(47);
a31mul(28) <= temp(46);
a31mul(27) <= temp(45);
a31mul(26) <= temp(44);
a31mul(25) <= temp(43);
a31mul(24) <= temp(42);
a31mul(23) <= temp(41);
a31mul(22) <= temp(40);
a31mul(21) <= temp(39);
a31mul(20) <= temp(38);
a31mul(19) <= temp(37);
a31mul(18) <= temp(36);
a31mul(17) <= temp(35);
a31mul(16) <= temp(34);
a31mul(15) <= temp(33);
a31mul(14) <= temp(32);
a31mul(13) <= temp(31);
a31mul(12) <= temp(30);
a31mul(11) <= temp(29);
a31mul(10) <= temp(28);
a31mul(9) <= temp(27);
a31mul(8) <= temp(26);
a31mul(7) <= temp(25);
a31mul(6) <= temp(24);
a31mul(5) <= temp(23);
a31mul(4) <= temp(22);
a31mul(3) <= temp(21);
a31mul(2) <= temp(20);
a31mul(1) <= temp(19);
a31mul(0) <= temp(18);



--a21mul <= a21*S1_1;
temp1 <= a21*S1_1;
a21mul(31) <= temp1(49);
a21mul(30) <= temp1(48);
a21mul(29) <= temp1(47);
a21mul(28) <= temp1(46);
a21mul(27) <= temp1(45);
a21mul(26) <= temp1(44);
a21mul(25) <= temp1(43);
a21mul(24) <= temp1(42);
a21mul(23) <= temp1(41);
a21mul(22) <= temp1(40);
a21mul(21) <= temp1(39);
a21mul(20) <= temp1(38);
a21mul(19) <= temp1(37);
a21mul(18) <= temp1(36);
a21mul(17) <= temp1(35);
a21mul(16) <= temp1(34);
a21mul(15) <= temp1(33);
a21mul(14) <= temp1(32);
a21mul(13) <= temp1(31);
a21mul(12) <= temp1(30);
a21mul(11) <= temp1(29);
a21mul(10) <= temp1(28);
a21mul(9) <= temp1(27);
a21mul(8) <= temp1(26);
a21mul(7) <= temp1(25);
a21mul(6) <= temp1(24);
a21mul(5) <= temp1(23);
a21mul(4) <= temp1(22);
a21mul(3) <= temp1(21);
a21mul(2) <= temp1(20);
a21mul(1) <= temp1(19);
a21mul(0) <= temp1(18);
 
--mul11 <= b2*E1_1;
temp2 <= b2*E1_1;
mul11(31) <= temp2(49);
mul11(30) <= temp2(48);
mul11(29) <= temp2(47);
mul11(28) <= temp2(46);
mul11(27) <= temp2(45);
mul11(26) <= temp2(44);
mul11(25) <= temp2(43);
mul11(24) <= temp2(42);
mul11(23) <= temp2(41);
mul11(22) <= temp2(40);
mul11(21) <= temp2(39);
mul11(20) <= temp2(38);
mul11(19) <= temp2(37);
mul11(18) <= temp2(36);
mul11(17) <= temp2(35);
mul11(16) <= temp2(34);
mul11(15) <= temp2(33);
mul11(14) <= temp2(32);
mul11(13) <= temp2(31);
mul11(12) <= temp2(30);
mul11(11) <= temp2(29);
mul11(10) <= temp2(28);
mul11(9) <= temp2(27);
mul11(8) <= temp2(26);
mul11(7) <= temp2(25);
mul11(6) <= temp2(24);
mul11(5) <= temp2(23);
mul11(4) <= temp2(22);
mul11(3) <= temp2(21);
mul11(2) <= temp2(20);
mul11(1) <= temp2(19);
mul11(0) <= temp2(18);


sum11 <= E1_0 + mul11;
sum12 <= sum11 + E1_2;
--mul12 <= G1*sum12;
temp3 <= G1*sum12;
mul12(31) <= temp3(49);
mul12(30) <= temp3(48);
mul12(29) <= temp3(47);
mul12(28) <= temp3(46);
mul12(27) <= temp3(45);
mul12(26) <= temp3(44);
mul12(25) <= temp3(43);
mul12(24) <= temp3(42);
mul12(23) <= temp3(41);
mul12(22) <= temp3(40);
mul12(21) <= temp3(39);
mul12(20) <= temp3(38);
mul12(19) <= temp3(37);
mul12(18) <= temp3(36);
mul12(17) <= temp3(35);
mul12(16) <= temp3(34);
mul12(15) <= temp3(33);
mul12(14) <= temp3(32);
mul12(13) <= temp3(31);
mul12(12) <= temp3(30);
mul12(11) <= temp3(29);
mul12(10) <= temp3(28);
mul12(9) <= temp3(27);
mul12(8) <= temp3(26);
mul12(7) <= temp3(25);
mul12(6) <= temp3(24);
mul12(5) <= temp3(23);
mul12(4) <= temp3(22);
mul12(3) <= temp3(21);
mul12(2) <= temp3(20);
mul12(1) <= temp3(19);
mul12(0) <= temp3(18);

sum13 <= mul12-a21mul;
Cell1_OUT <= sum13-a31mul;

S1_1 <= Cell1_OUT;

  --   ------------------ Section 2 ------------------
E2_0 <= S1_1;

--a32mul <= a32*S2_2;
temp2 <= a32*S2_2;
a32mul(31) <= temp02(49);
a32mul(30) <= temp02(48);
a32mul(29) <= temp02(47);
a32mul(28) <= temp02(46);
a32mul(27) <= temp02(45);
a32mul(26) <= temp02(44);
a32mul(25) <= temp02(43);
a32mul(24) <= temp02(42);
a32mul(23) <= temp02(41);
a32mul(22) <= temp02(40);
a32mul(21) <= temp02(39);
a32mul(20) <= temp02(38);
a32mul(19) <= temp02(37);
a32mul(18) <= temp02(36);
a32mul(17) <= temp02(35);
a32mul(16) <= temp02(34);
a32mul(15) <= temp02(33);
a32mul(14) <= temp02(32);
a32mul(13) <= temp02(31);
a32mul(12) <= temp02(30);
a32mul(11) <= temp02(29);
a32mul(10) <= temp02(28);
a32mul(9) <= temp02(27);
a32mul(8) <= temp02(26);
a32mul(7) <= temp02(25);
a32mul(6) <= temp02(24);
a32mul(5) <= temp02(23);
a32mul(4) <= temp02(22);
a32mul(3) <= temp02(21);
a32mul(2) <= temp02(20);
a32mul(1) <= temp02(19);
a32mul(0) <= temp02(18);



--a22mul <= a22*S2_1; 
temp12 <= a22*S2_1;
a22mul(31) <= temp12(49);
a22mul(30) <= temp12(48);
a22mul(29) <= temp12(47);
a22mul(28) <= temp12(46);
a22mul(27) <= temp12(45);
a22mul(26) <= temp12(44);
a22mul(25) <= temp12(43);
a22mul(24) <= temp12(42);
a22mul(23) <= temp12(41);
a22mul(22) <= temp12(40);
a22mul(21) <= temp12(39);
a22mul(20) <= temp12(38);
a22mul(19) <= temp12(37);
a22mul(18) <= temp12(36);
a22mul(17) <= temp12(35);
a22mul(16) <= temp12(34);
a22mul(15) <= temp12(33);
a22mul(14) <= temp12(32);
a22mul(13) <= temp12(31);
a22mul(12) <= temp12(30);
a22mul(11) <= temp12(29);
a22mul(10) <= temp12(28);
a22mul(9) <= temp12(27);
a22mul(8) <= temp12(26);
a22mul(7) <= temp12(25);
a22mul(6) <= temp12(24);
a22mul(5) <= temp12(23);
a22mul(4) <= temp12(22);
a22mul(3) <= temp12(21);
a22mul(2) <= temp12(20);
a22mul(1) <= temp12(19);
a22mul(0) <= temp12(18);



--mul21 <= b2*E2_1;
temp22 <= b2*E2_1;
mul21(31) <= temp22(49);
mul21(30) <= temp22(48);
mul21(29) <= temp22(47);
mul21(28) <= temp22(46);
mul21(27) <= temp22(45);
mul21(26) <= temp22(44);
mul21(25) <= temp22(43);
mul21(24) <= temp22(42);
mul21(23) <= temp22(41);
mul21(22) <= temp22(40);
mul21(21) <= temp22(39);
mul21(20) <= temp22(38);
mul21(19) <= temp22(37);
mul21(18) <= temp22(36);
mul21(17) <= temp22(35);
mul21(16) <= temp22(34);
mul21(15) <= temp22(33);
mul21(14) <= temp22(32);
mul21(13) <= temp22(31);
mul21(12) <= temp22(30);
mul21(11) <= temp22(29);
mul21(10) <= temp22(28);
mul21(9) <= temp22(27);
mul21(8) <= temp22(26);
mul21(7) <= temp22(25);
mul21(6) <= temp22(24);
mul21(5) <= temp22(23);
mul21(4) <= temp22(22);
mul21(3) <= temp22(21);
mul21(2) <= temp22(20);
mul21(1) <= temp22(19);
mul21(0) <= temp22(18);

sum21 <= E2_0 + mul21;
sum22 <= sum21 + E2_2;
--mul22 <= G2*sum22;
temp32 <= G2*sum22;
mul22(31) <= temp32(49);
mul22(30) <= temp32(48);
mul22(29) <= temp32(47);
mul22(28) <= temp32(46);
mul22(27) <= temp32(45);
mul22(26) <= temp32(44);
mul22(25) <= temp32(43);
mul22(24) <= temp32(42);
mul22(23) <= temp32(41);
mul22(22) <= temp32(40);
mul22(21) <= temp32(39);
mul22(20) <= temp32(38);
mul22(19) <= temp32(37);
mul22(18) <= temp32(36);
mul22(17) <= temp32(35);
mul22(16) <= temp32(34);
mul22(15) <= temp32(33);
mul22(14) <= temp32(32);
mul22(13) <= temp32(31);
mul22(12) <= temp32(30);
mul22(11) <= temp32(29);
mul22(10) <= temp32(28);
mul22(9) <= temp32(27);
mul22(8) <= temp32(26);
mul22(7) <= temp32(25);
mul22(6) <= temp32(24);
mul22(5) <= temp32(23);
mul22(4) <= temp32(22);
mul22(3) <= temp32(21);
mul22(2) <= temp32(20);
mul22(1) <= temp32(19);
mul22(0) <= temp32(18);


sum23 <= mul22-a22mul;
Cell1_OUT <= sum23-a32mul;

Output_REG <= Cell1_OUT;
S2_1 <= Output_REG;

    END IF; 
  END PROCESS input_reg_process;
end Behavioral;

**inoxxam** · 26/09/2014, 22h17

Bonjour,
Premièrement il n'est pas de très bon usage d'utiliser STD_LOGIC_ARITH et STD_LOGIC_UNSIGNED conjointement avec numeric_std. D'ailleurs, je te conseille d'oublier STD_LOGIC_ARITH et STD_LOGIC_UNSIGNED et de n'utiliser que numeric_std pour tes designs, ça t'éviteras des soucis.
Tu peux essayer la ligne suivante, qui est en principe propre:
result = std_logic_vector(unsigned(a)*u nsigned(b))
Sinon pourrais-tu nous dire quelles erreurs tu as exactement?

**jiherve** · 27/09/2014, 19h48

Bonsoir,
Quel charabia!
Le VHDL ne sait pas manipuler les entiers plus grands que 32 bits [0x80000001.. 0x7FFFFFFF].
ensuite:
mul22(31) <= temp32(49);
....
mul22(0) <= temp32(18);
peut s’écrire : mul22(31 downto 0)<= temp32(49 downto 18);
c'est tout de même plus compact.
Donc tu réécris et ensuite on en reparle.
JR

**ykhalildie** · 27/09/2014, 21h47

Messieurs Dames,

Merci pour vos commentaires.

Il n'y a plus d'erreur lors de la simulation. Vous pouvez imaginer que le signal de sortie n'est pas encore celui désiré...

Mon problème se trouve plutôt au niveau de la forme; en gros, l'algorithme (très simple) à implémenter est le suivant:

$\text{[math]}$ pour la première section;

le signal de sortie de la première section est le signal d'entrée de la 2^ème section.

$\text{[math]}$ pour la première section;

Ce filtre à pour but le calcul de la valeur moyenne du signal d'entrée.

Merci pour vos commentaires sur cette 2^nd version.

-Ykhalildie

Voici la nouvelle version du code:

Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;



entity Filter1_Vo is
port (
    Filter_IN : in STD_LOGIC_VECTOR (31 DOWNTO 0);
    Filter_OUT : out STD_LOGIC_VECTOR (31 DOWNTO 0);
    RST : in STD_LOGIC;
    CLK_Filter : in STD_LOGIC
);
end Filter1_Vo;
architecture Behavioral of Filter1_Vo is

  CONSTANT G1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011110101010011001"; 
  CONSTANT a21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011100111111111111"; 
  CONSTANT a31 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000011101110110000100"; 
  CONSTANT G2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000010110010011000001"; 
  CONSTANT a22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000010101000011011111"; 
  CONSTANT a32 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000100001000100011"; 
  CONSTANT b2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000010000000000000000000";
  
  SIGNAL Input_REG : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";  
  SIGNAL Cell1_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL Output_REG : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";  

  SIGNAL temp : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp1 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp3 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp4 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp5 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp6 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp7 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";


  SIGNAL temp02 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp12 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp32 : STD_LOGIC_VECTOR (63 DOWNTO 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  SIGNAL temp42 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp52 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp62 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL temp72 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";


  SIGNAL E1_0 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E1_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E1_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S1_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S1_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL E2_0 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E2_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL E2_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S2_1 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL S2_2 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL a31mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL a21mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul11 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum11 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum12 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul12 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum13 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

  SIGNAL a32mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL a22mul : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum21 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL mul22 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";
  SIGNAL sum23 : STD_LOGIC_VECTOR (31 DOWNTO 0) := "00000000000000000000000000000000";

begin

input_reg_process : PROCESS (CLK_Filter, RST)
  BEGIN
    IF RST = '0' THEN
        Cell1_OUT <= "00000000000000000000000000000000";
        Output_REG <= "00000000000000000000000000000000";
        Input_REG <= "00000000000000000000000000000000";
        E1_0 <= "00000000000000000000000000000000";
        E1_1 <= "00000000000000000000000000000000";
        E1_2 <= "00000000000000000000000000000000";
        E2_0 <= "00000000000000000000000000000000";
        E2_1 <= "00000000000000000000000000000000";
        E2_2 <= "00000000000000000000000000000000";
        S1_1 <= "00000000000000000000000000000000";
        S1_2 <= "00000000000000000000000000000000";
        S2_1 <= "00000000000000000000000000000000";
        S2_2 <= "00000000000000000000000000000000";
    ELSIF CLK_Filter'event AND CLK_Filter = '1' THEN
        E1_0 <= Filter_IN;
        E1_2 <= E1_1;
        E1_1 <= E1_0;
        S1_2 <= S1_1;
        
        E2_2 <= E2_1;
        E2_1 <= E2_0;
        S2_2 <= S2_1;
        



     ------------------ Section 1 ------------------

--a31mul <= a31*S1_2;
temp <= STD_LOGIC_VECTOR(signed(a31) * signed(S1_2));
a31mul(31) <= temp(63);
a31mul(30 downto 0)<= temp(48 downto 18);

--a21mul <= a21*S1_1;
temp1 <= STD_LOGIC_VECTOR(signed(a21)*signed(S1_1));
a21mul(31) <= temp1(63);
a21mul(30 downto 0)<= temp1(48 downto 18);
 
--mul11 <= b2*E1_1;
temp2 <= STD_LOGIC_VECTOR(signed(E1_1)+signed(E1_1));
mul11 <= temp2;

temp4 <= STD_LOGIC_VECTOR(signed(E1_0) + signed(mul11));
sum11 <= temp4;

temp5 <= STD_LOGIC_VECTOR(signed(sum11) + signed(E1_2));
sum12 <= temp5;

--mul12 <= G1*sum12;
temp3 <= STD_LOGIC_VECTOR(signed(G1)*signed(sum12));
mul12(31) <= temp3(63);
mul12(30 downto 0)<= temp3(48 downto 18);

temp6 <= STD_LOGIC_VECTOR(signed(mul12)-signed(a21mul));
sum13 <= temp6;

temp7 <= STD_LOGIC_VECTOR(signed(sum13)-signed(a31mul));
S1_1 <= temp7;

  --   ------------------ Section 2 ------------------
E2_0 <= S1_1;

--a32mul <= a32*S2_2;
temp02 <= STD_LOGIC_VECTOR(signed(a32)*signed(S2_2));
a32mul(31) <= temp02(63);
a32mul(30 downto 0)<= temp02(48 downto 18);


--a22mul <= a22*S2_1; 
temp12 <= STD_LOGIC_VECTOR(signed(a22)*signed(S2_1));
a22mul(31) <= temp12(63);
a22mul(30 downto 0)<= temp12(48 downto 18);


--mul21 <= b2*E2_1;
temp22 <= STD_LOGIC_VECTOR(signed(E2_1)+signed(E2_1));
mul21 <= temp22;

temp42 <= STD_LOGIC_VECTOR(signed(E2_0) + signed(mul21));
sum21 <= temp42;

temp52 <= STD_LOGIC_VECTOR(signed(sum21) + signed(E2_2));
sum22 <= temp52;

--mul22 <= G2*sum22;
temp32 <= STD_LOGIC_VECTOR(signed(G2)*signed(sum22));
mul22(31 downto 0)<= temp32(49 downto 18);
mul22(31) <= temp32(63);
mul22(30 downto 0)<= temp32(48 downto 18);

temp62 <= STD_LOGIC_VECTOR(signed(mul22)-signed(a22mul));
sum23 <= temp62;

temp72 <= STD_LOGIC_VECTOR(signed(sum23)-signed(a32mul));
S2_1 <= temp72;

Output_REG <= S2_1;

    END IF; 
  END PROCESS input_reg_process;
end Behavioral;

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**albanxiii** · 28/09/2014, 10h26

Bonjour,

Code:

E1_0 <= "00000000000000000000000000000000";

s'écrit de façon plus compacte

Code:

E1_0 <= (others => '0');

On vous impose de coder votre filtre en VHDL ou vous pouvez utiliser des outils du style "High Level Synthesis" ?

@+

**ykhalildie** · 28/09/2014, 10h30

Hi Sir,

Merci pour ce commentaire, oui le VHDL m'est imposé.

@+

Code VHDL Digital filter (issue with multiplication)

Code VHDL Digital filter (issue with multiplication)

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