Bonjour,
Je ne comprend pas la page 314 de ce datasheet :
http://ww1.microchip.com/downloads/e...Doc/41412F.pdf
Je cherche à obtenir une interruption à chaque changement d'état de C1OUT mais j'ai un fonctionnement aléatoire des interruptions , je pense que je configure mal quelque chose , mais je ne comprend pas ce paragraphe :
Par avance merci pour votre aide.18.4 Comparator Interrupt Operation
The comparator interrupt flag will be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor
gate (see Figure 18-2). The first latch is updated with
the comparator output value, when the CMxCON0
register is read or written. The value is latched on the
third cycle of the system clock, also known as Q3. This
first latch retains the comparator value until another
read or write of the CMxCON0 register occurs or a
Reset takes place. The second latch is updated with
the comparator output value on every first cycle of the
system clock, also known as Q1. When the output
value of the comparator changes, the second latch is
updated and the output values of both latches no
longer match one another, resulting in a mismatch
condition. The latch outputs are fed directly into the
inputs of an exclusive-or gate. This mismatch condition
is detected by the exclusive-or gate and sent to the
interrupt circuitry. The mismatch condition will persist
until the first latch value is updated by performing a
read of the CMxCON0 register or the comparator
output returns to the previous state.
When the mismatch condition occurs, the comparator
interrupt flag is set. The interrupt flag is triggered by the
edge of the changing value coming from the exclusiveor
gate. This means that the interrupt flag can be reset
once it is triggered without the additional step of reading
or writing the CMxCON0 register to clear the mismatch
latches. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures 18-3
and 18-4.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE/GIEL and GIE/GIEH bits of
the INTCON register must all be set to enable comparator
interrupts. If any of these bits are cleared, the interrupt
is not enabled, although the CxIF bit of the PIR2
register will still be set if an interrupt condition occurs.
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