Modelsim signal disparu

[invite68aa31e7]

Bonjour,

je viens de coder une fifo permettant de convertir un bus de 16 bits en un bus de 32 bits . mais j'ai un probleme au moment des simu. En effet un des signaux de mon testbench n'apparait pas dans la simu alors qu'il devrait et malgré la valeur que je lui applique, il se comporte comme une horloge je ne comprends pas . j'ai essayé de lui assigné une valeur au moment de la description du du signal puis de faire changer sa valeur dans un process mais rien n'y fait , il n'apparait pas et fait ce qu'il veut. Il s'agit du signal wr_en_in_t. Voici le testbench en question:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fifo_conversion_bench is
end fifo_conversion_bench;

architecture TB of fifo_conversion_bench is



signal clock_in_t : std_logic;
signal wr_en_in_t : std_logic ;
signal rd_en_in_t : std_logic;
signal write_data_in_t : std_logic_vector ( 15 downto 0 );
signal read_data_out_t : std_logic_vector( 31 downto 0 );
signal reset_t : std_logic:='1';
signal full_out_t : std_logic;
signal empty_out_t : std_logic;
signal StopClock : boolean := FALSE;



component fifo_16_32 is
port (
clock_in : IN std_logic;
wr_en_in : IN std_logic;
rd_en_in : IN std_logic;
write_data_in : IN std_logic_vector ( 15 downto 0 );
read_data_out : OUT std_logic_vector( 31 downto 0 );
reset : IN std_logic :='1';
full_out : OUT std_logic;
empty_out : OUT std_logic
);
end component;


begin


reset_t <= '0' after 25 ns;


fifo : fifo_16_32
port map (clock_in => clock_in_t,
wr_en_in => clock_in_t,
rd_en_in => rd_en_in_t,
write_data_in => write_data_in_t,
read_data_out => read_data_out_t,
reset => reset_t,
full_out => full_out_t,
empty_out => empty_out_t
);

ClockGen: process is
begin
while not StopClock loop
clock_in_t <= '0';
wait for 5 ns;
clock_in_t <= '1';
wait for 5 ns;
end loop;
wait;
end process ClockGen;

sim : process is

begin

wait until rising_edge(clock_in_t);
wr_en_in_t <= '0';
rd_en_in_t <= '0';
write_data_in_t <= "0000000000000000";

wait until rising_edge(clock_in_t);
wr_en_in_t <= '1' ;
rd_en_in_t <= '0';
write_data_in_t <= "0000000000000001";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '0' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000000010";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '1' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000000011";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '1' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000000100";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '1' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000000110";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '1' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000000111";

wait until rising_edge(clock_in_t);

wr_en_in_t <= '1' ;
rd_en_in_t <= '1';
write_data_in_t <= "0000000000001000";



end process sim;

end TB;
-----

[jiherve]

Bonjour,
1 : tu n'utilises pas ce signal, mais normalement Modelsim aurait du te le garder tout de même , relis ton code!
fifo : fifo_16_32
port map (...
wr_en_in => clock_in_t,
....
);
bien sur si ce que tu regardes c'est "wr_en_in" alors tout s'explique.
2 : c'est trés cochon
il eu fallut écrire:

sim : process(clock_in_t,reset_t)
  begin
    if reset_t = '1' then
      wr_en_in_t <= '0';
      rd_en_in_t <= '0';
      write_data_in_t <=(others => '0' );
   elsif  rising_edge(clock_in_t) then
     wr_en_in_t <= '1' ;-- ecrire la logique souhaitée
     rd_en_in_t <= '0';--  ecrire la logique souhaitée
     write_data_in_t <= std_logic_vector(unsigned(write_data_in_t )+1) ;-- par exemple
   end if;
end process sim;

avantage tant que l'horloge tourne cela tourne aussi et c'est moins fastidieux à écrire et en plus c'est synthétisable!
JR

[invite68aa31e7]

merci beaucoup c'était une erreur de copier-coller. cela dit je ne comprends pas car je n'obtiens pas de signal en sortie de ma fifo. pourriez vous m'aider encore une fois?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


library unisim;
use unisim.all;

entity fifo_16_32 is
port (
clock_in : IN std_logic;
wr_en_in : IN std_logic;
rd_en_in : IN std_logic;
write_data_in : IN std_logic_vector ( 15 downto 0 );
read_data_out : OUT std_logic_vector( 31 downto 0 );
reset : IN std_logic;
full_out : OUT std_logic;
empty_out : OUT std_logic
);
end fifo_16_32;

architecture fifoctrl of fifo_16_32 is

signal clock : std_logic;
signal clock_fb : std_logic;
signal clock_in_buf : std_logic;
signal locked : std_logic;
-- signal clock_fb_buf : std_logic;

signal wr_en : std_logic;
signal wr_en_b : std_logic;
signal rd_en : std_logic;
signal read_data : std_logic_vector ( 31 downto 0 );
signal write_data : std_logic_vector ( 15 downto 0 );
signal fifor : std_logic;
signal full : std_logic;
signal empty : std_logic;
signal carry : std_logic;
signal th : std_logic;

subtype bit32 is std_logic_vector ( 31 downto 0 );
type vector32 is array ( 0 to 7 ) of bit32;
signal write_data_buf : vector32;

signal counterR : integer range 0 to 7;
signal counterW : integer range 0 to 7;

component IBUF
port (
O : out std_logic;
I : in std_logic
);
end component;

component OBUF
port (
O : out std_logic;
I : in std_logic
);
end component;

component CLKDLL
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;

component BUFG
port (
I : IN std_logic;
O : OUT std_logic
);
end component;

component IBUFG
port (
I : IN std_logic;
O : OUT std_logic
);
end component;


begin

cibuf0 : IBUFG port map (I => clock_in, O => clock_in_buf);
cbuf1 : BUFG port map (I => clock, O => clock_fb);


clockdll : CLKDLL port map (CLK0 => open, CLK90 => open, CLK180 => open, CLK270 => open,
CLK2x => clock, CLKDV => open, LOCKED => locked, CLKIN => clock_in_buf,
CLKFB => clock_fb, RST => fifor);

ibuf0 : IBUF port map (O => fifor, I => reset);
ibuf1 : IBUF port map (O => wr_en_b, I => wr_en_in);
ibuf2 : IBUF port map (O => rd_en, I => rd_en_in);
ibuf3 : IBUF port map (O => write_data(0), I => write_data_in(0));
ibuf4 : IBUF port map (O => write_data(1), I => write_data_in(1));
ibuf5 : IBUF port map (O => write_data(2), I => write_data_in(2));
ibuf6 : IBUF port map (O => write_data(3), I => write_data_in(3));
ibuf7 : IBUF port map (O => write_data(4), I => write_data_in(4));
ibuf8 : IBUF port map (O => write_data(5), I => write_data_in(5));
ibuf9 : IBUF port map (O => write_data(6), I => write_data_in(6));
ibuf10 : IBUF port map (O => write_data(7), I => write_data_in(7));
ibuf11 : IBUF port map (O => write_data(8), I => write_data_in(8));
ibuf12 : IBUF port map (O => write_data(9), I => write_data_in(9));
ibuf13 : IBUF port map (O => write_data(10), I => write_data_in(10));
ibuf14 : IBUF port map (O => write_data(11), I => write_data_in(11));
ibuf15 : IBUF port map (O => write_data(12), I => write_data_in(12));
ibuf16 : IBUF port map (O => write_data(13), I => write_data_in(13));
ibuf17 : IBUF port map (O => write_data(14), I => write_data_in(14));
ibuf18 : IBUF port map (O => write_data(15), I => write_data_in(15));




obuf0 : OBUF port map (O => read_data_out(0), I => read_data(0));
obuf1 : OBUF port map (O => read_data_out(1), I => read_data(1));
obuf2 : OBUF port map (O => read_data_out(2), I => read_data(2));
obuf3 : OBUF port map (O => read_data_out(3), I => read_data(3));
obuf4 : OBUF port map (O => read_data_out(4), I => read_data(4));
obuf5 : OBUF port map (O => read_data_out(5), I => read_data(5));
obuf6 : OBUF port map (O => read_data_out(6), I => read_data(6));
obuf7 : OBUF port map (O => read_data_out(7), I => read_data(7));
obuf8 : OBUF port map (O => read_data_out(8), I => read_data(8));
obuf9 : OBUF port map (O => read_data_out(9), I => read_data(9));
obuf10: OBUF port map (O => read_data_out(10), I => read_data(10));
obuf11: OBUF port map (O => read_data_out(11), I => read_data(11));
obuf12: OBUF port map (O => read_data_out(12), I => read_data(12));
obuf13: OBUF port map (O => read_data_out(13), I => read_data(13));
obuf14: OBUF port map (O => read_data_out(14), I => read_data(14));
obuf15: OBUF port map (O => read_data_out(15), I => read_data(15));
obuf16 : OBUF port map (O => read_data_out(16), I => read_data(16));
obuf17 : OBUF port map (O => read_data_out(17), I => read_data(17));
obuf18 : OBUF port map (O => read_data_out(18), I => read_data(18));
obuf19 : OBUF port map (O => read_data_out(19), I => read_data(19));
obuf20 : OBUF port map (O => read_data_out(20), I => read_data(20));
obuf21 : OBUF port map (O => read_data_out(21), I => read_data(21));
obuf22 : OBUF port map (O => read_data_out(22), I => read_data(22));
obuf23 : OBUF port map (O => read_data_out(23), I => read_data(23));
obuf24 : OBUF port map (O => read_data_out(24), I => read_data(24));
obuf25 : OBUF port map (O => read_data_out(25), I => read_data(25));
obuf26: OBUF port map (O => read_data_out(26), I => read_data(26));
obuf27: OBUF port map (O => read_data_out(27), I => read_data(27));
obuf28: OBUF port map (O => read_data_out(28), I => read_data(28));
obuf29: OBUF port map (O => read_data_out(29), I => read_data(29));
obuf30: OBUF port map (O => read_data_out(30), I => read_data(30));
obuf31: OBUF port map (O => read_data_out(31), I => read_data(31));



obuf32: OBUF port map (O => full_out, I => full);
obuf33: OBUF port map (O => empty_out, I => empty);

proc0 : process (clock, fifor)
begin
if (fifor = '1') then
counterW <= 0;
elsif rising_edge(clock) then
if ( locked = '1' ) then
if(full = '0' AND wr_en = '1') then
if(th = '0') then
write_data_buf(counterW)(31 downto 16) <= write_data;
else
write_data_buf(counterW)(15 downto 0) <= write_data;
counterW <= counterW + 1;
end if;
end if;
end if;
end if;
end process proc0;

proc1 : process (clock_in_buf, fifor)
begin
if ( fifor = '1' ) then
counterR <= 0;
elsif rising_edge(clock_in_buf) then
if(locked = '1') then
if (empty = '0' AND th = '0' AND rd_en = '1') then
read_data <= write_data_buf(counterR);
counterR <= counterR + 1;
end if;
end if;
end if;
end process proc1;

proc2 : process (clock_in_buf, fifor)
begin
if (fifor = '1') then
full <= '0';
empty <= '1';
elsif rising_edge(clock_in_buf) then
if (locked = '1') then
if((counterW - counterR = 1) AND carry = '0' AND rd_en = '1')then
empty <= '1';
elsif(((counterW = 7 and counterR = 6) OR (counterW = 0 and counterR = 7)) AND carry = '1' AND rd_en = '1') then
empty <= '1';
elsif (empty = '1' AND wr_en = '0') then
empty <= '1';
else
empty <= '0';
end if;

-- if(((counterR - counterW = 1) OR (counterR = 0 and counterW = 0)) AND carry = '1' AND wr_en = '1') then
-- full <= '1';
-- elsif ((counterR = 7 and counterW = 6) and carry = '0' AND wr_en = '1') then
-- full <= '1';
-- elsif (full = '1' AND rd_en = '0') then
-- full <= '1';
-- else
-- full <= '0';
-- end if;

if((counterR - counterW = 1) AND carry = '1' AND wr_en = '1') then
full <= '1';
elsif (((counterR = 7 and counterW = 6) OR (counterR = 0 and counterW = 7)) and carry = '0' AND wr_en = '1') then
full <= '1';
elsif (full = '1' AND rd_en = '0') then
full <= '1';
else
full <= '0';
end if;

end if;
end if;
end process proc2;

proc3 : process (clock_in_buf, fifor)
begin
if(fifor = '1') then
carry <= '0';
elsif rising_edge(clock_in_buf) then
if (locked = '1') then
if((counterR = 7 AND rd_en = '1' AND empty = '0') OR (counterW = 7 AND wr_en = '1' AND full = '0')) then
carry <= NOT carry;
end if;
end if;
end if;
end process proc3;

proc4 : process (clock, fifor)
begin
if(fifor = '1') then
th <= '1';
elsif rising_edge(clock) then
if (locked = '1') then
th <= NOT th;
end if;
end if;
end process proc4;

proc5 : process (clock_in_buf)
begin
if rising_edge(clock_in_buf) then
wr_en <= wr_en_b;
end if;
end process proc5;

end fifoctrl;

[jiherve]

Bonsoir,
Là tu en demandes un peu trop, je fais du VHDL plus de 10 h/j , je veux bien aider un peu mais bosser gratos non, surtout que là c'est du projet commercial où je me trompe!
Désolé.
JR

[A voir en vidéo sur Futura]