Bonjour à tous,
Dans un projet VHDL, je doit afficher la valeur de l'entrée sur la console de NIOS2, mais je n'arrive pas, la partie vhdl (sans la partie bus avalon) marchait bien sur un oscilo, mais en ajoutant la partie bus avalon le code se complie sans erreurs et sur la console de NIOS2 il affiche toujours -1 Hz. Est ce que quelqu'un peut m'aider à resoudre ce problème.
merci
code VHDL
code NIOS2Code:library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity gestion_anemometre is port ( clk, chipselect, write_n, reset_n, address : in std_logic; in_freq_anemometre : in std_logic; writedata : in std_logic_vector (31 downto 0); readdata : out std_logic_vector (31 downto 0) ); end entity; architecture arch of gestion_anemometre is signal count : integer:=1; signal tmp : std_logic := '0'; signal temp : std_logic_vector ( 7 downto 0); signal temp1 : std_logic_vector ( 7 downto 0); signal temp2 : std_logic_vector ( 7 downto 0); signal clk_1hz : std_logic; signal nbr_front : std_logic_vector(7 downto 0); TYPE State_type IS (init, cont, mono,acq); SIGNAL State : State_Type; signal tmp1 : std_logic; signal tmp2 : std_logic_vector(7 downto 0); signal config : std_logic_vector(2 downto 0); signal code : std_logic_vector(9 downto 0); signal clk_50M: std_logic; signal start_stop : std_logic; signal raz_n : std_logic; signal continu : std_logic; signal data_anemometre : std_logic_vector(7 downto 0); signal data_valid : std_logic; begin -------------------------------------------------process diviseur de frequence----------------------- clk_50M<= clk; process(Clk_50M,raz_n) begin if(raz_n='0') then count<=1; tmp<='0'; elsif(Clk_50M'event and Clk_50M='1') then count <=count+1; if (count = 25) then tmp <= NOT tmp; count <= 1; end if; end if; clk_1hz <= tmp; end process; -------------------------------------------------process compteur----------------------------------- process(Clk_1hz,in_freq_anemometre,raz_n) begin if raz_n = '0' then temp<= (others=>'0'); elsif(in_freq_anemometre = '1' and in_freq_anemometre'event)then if(Clk_1hz = '1')then temp <= temp + 1; else temp <= (others => '0'); end if; end if; end process; process(Clk_1hz,raz_n) begin if raz_n = '0' then temp2<= (others=>'0'); elsif(falling_edge(in_freq_anemometre) )then if(Clk_1hz = '1')then temp2 <= temp2 + 1; else temp2 <= (others => '0'); end if; end if; end process; process(Clk_1hz,raz_n) begin if raz_n= '0' then temp1<= (others=>'0'); elsif (falling_edge(clk_1hz))then temp1 <= temp+temp2; end if; end process; Nbr_front <= temp1; ------------------------------------------------process machine à états---------------------------- process(raz_n,clk_50M) begin if (raz_n='0') then tmp1 <='0'; tmp2 <=(others=> '0'); state <=init; elsif rising_edge(clk_50M)then case state is when init => if (continu='1') then state <= cont; else state <= mono; end if; when cont => if (continu='0') then state <= mono; end if; tmp1 <= '1'; tmp2 <= nbr_front; when mono => if (continu='1') then state <= cont; elsif(start_stop= '1')then state <= acq; end if; tmp2 <=(others=> '0'); tmp1 <= '0'; when acq => if (start_stop= '0')then state <= mono; end if; tmp1 <= '1'; tmp2 <= nbr_front; when others => state <= init; end case; end if; end process; Data_anemometre <= tmp2; data_valid <= tmp1; -------------------------------------------------process ecriture avalon---------------------------- raz_n <= config(0); continu <= config(1); start_stop <= config(2); data_valid<=code(8); data_anemometre(7)<=code(7); data_anemometre(6)<=code(6); data_anemometre(5)<=code(5); data_anemometre(4)<=code(4); data_anemometre(3)<=code(3); data_anemometre(2)<=code(2); data_anemometre(1)<=code(1); data_anemometre(0)<=code(0); registers: process (clk, reset_n) begin if reset_n = '0' then config <= (others => '0'); elsif clk'event and clk = '1' then if chipselect ='1' and write_n = '0' then if address = '0' then config <= (writedata (2 downto 0)); else code <= (writedata (9 downto 0)); end if; end if; end if; end process registers; process_Read: PROCESS(address, config, data_valid, data_anemometre) BEGIN case address is when '0' => readdata <= X"0000000"&'0'&config; when '1' => readdata <=X"00000"&"00"&code; when others => readdata <= (others => '0'); end case; END PROCESS process_Read; end arch;
Code:#include "sys/alt_stdio.h" #include "system.h" #include "unistd.h" #include <stdio.h> #define freq (unsigned int *)AVALON_PWM_0_BASE #define duty (unsigned int *)(AVALON_PWM_0_BASE+4) #define control (unsigned int *)(AVALON_PWM_0_BASE+8) #define config (unsigned int *)GESTION_ANEMOMETRE_0_BASE #define code (unsigned int *) (GESTION_ANEMOMETRE_0_BASE+4) int main() { alt_putstr("Hello from Nios II!\n"); /*******************pwm**********************************************/ *freq = 0x2FDEF; // divise clk par 196079 pour avoir une frequence de sortie de 255 hz *duty = 0x0200; // RC = 50% *control = 0x3; /*************************anemometre******************************/ *config=0x3; unsigned int *data_anemometre = *code & 0xFF; unsigned int *data_valid = (*code << 9) &1; /* Event loop never exits. */ printf ("%d\n ",*data_valid); while (1) { printf ("%d hz\n ",*data_anemometre); usleep(1000000); } return 0; }
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